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VHDL四位全加器三种语言编程

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四位全加器的三种 VHDL 语言描述方式:

一:数据流描述方式
libraryieee; use ieee.std_logic_1164.all; entity add1 is port(a,b,cin:instd_logic; s,cout:outstd_logic); end add1; architecture dataflow of add1 is begin s<=(a xor b) xorcin; cout<=((a xor b)and cin)or(a and b); end dataflow;

二:行为描述方式
libraryieee; use ieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entity add22 is port(a,b,cin:instd_logic; s,co:outstd_logic); end add22; architecture dataflow of add22 is signaltmp:std_logic; begin process(a,b,cin) variable n:integer range 0 to 3; constants_vector: std_logic_vector(3 downto 0):="1010"; constantco_vector: std_logic_vector(3 downto 0):="1100"; begin n:=0; if a='1' then n:=n+1; end if; if b='1' then n:=n+1; end if; ifcin='1' then n:=n+1; end if; s<=s_vector(n) after 10 ;

co<=co_vector(n); end process; end dataflow;

三:结构描述方式
Library ieee; Use ieee.std_logic_1164.all; Entity and_2 is port(a,b: in std_logic; c: out std_logic); End and_2; Architecture behave of and_2 is begin c<= (a and b); End behave; Library ieee; Use ieee.std_logic_1164.all; Entity or_2 is port(a,b: in std_logic; c: out std_logic); End or_2; Architecture behave of or_2 is begin c<= (a or b); End behave; Library ieee; Use ieee.std_logic_1164.all; Entity xor_2 is port(a,b: in std_logic; c: out std_logic); End xor_2; Architecture behave of xor_2 is begin c<= (a xor b); End behave; Library ieee; Use ieee.std_logic_1164.all; Entity add33 is port(A,B,Cin: in std_logic; Co,S: out std_logic); End add33; Architecture structure of add33 is component and_2

port(a,b: in std_logic; c: out std_logic); End component; component or_2 port(a,b: in std_logic; c: out std_logic); End component; component xor_2 port(a,b: in std_logic; c: out std_logic); End component; signal tmp1,tmp2,tmp3:std_logic; begin u1:xor_2 port map(A,B,tmp1); u2:and_2 port map(tmp1,Cin,tmp2); u3:xor_2 port map(tmp1,Cin,S); u4:and_2 port map(A,B,tmp3); u5:or_2 port map(tmp2,tmp3,Co); End structure;




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